The present invention is directed to an ECL-CMOS converter for converting ECL back to CMOS levels.
ECL and CMOS circuits are used extensively in semiconductor circuit technology. The ECL (emittercoupled logic) circuits have the shortest switching times of all logic families. These switching times lie in the area of a few nanoseconds and may also extend to below one nanosecond. Complimentary MOSFET transistors are utilized in CMOS circuits. The ohmic output load of the CMOS circuits is extremely low because of the high input impedances. The switching time increases with a higher capacitative output load. Given a high capacitative output load, the switching time can have an order of magnitude of about 10 ns and above.
In addition to MOS circuit technology, a bipolar CMOS (BICMOS) circuit technology has been recently developed that is particularly useful in time-critical and compact circuits. Advantages from MOS circuit technology as well as from bipolar circuit technology are due to the use of BICMOS circuits. High packing densities and low static dissipated power are characteristic of circuits composed of CMOS circuit technology, whereas low offset voltage and extremely high processing speed are characteristic of circuits in ECL or bipolar circuit technology. These characteristics are features that make use of circuits in "BICMOS" circuit technology desireable. Extremely high operating speeds can be achieved with the use of "BICMOS" circuit technology because the circuit portions having higher processing speeds are realized in ECL circuit technology but less time-critical circuit portions are realized in CMOS circuit technology. Fast level converters are required between these two circuit portions or blocks, whereby the conversion of ECL level into CMOS level is more technically difficult to realize than a reverse conversion of CMOS level into ECL level.
FIG. 1 shows a prior art ECL-CMOS converter wherein, first, a bipolar differential amplifier is utilized in order to amplify the ECL level to an intermediate level. This level is set by the selection of one or more collector resistors. Further amplification to the CMOS level is effected by a CMOS circuit. A CMOS differential amplifier or a CMOS inverter stage can be used for this purpose, whereby the necessary level matching is achieved with emitter followers or level shifters, which uses additional power. The circuit shown in FIG. 1 is composed of a bipolar, asymmetrical differential amplifier that acts as voltage amplifier, of a following stage of an emitter follower (also referred to as a level shifter) and of a CMOS output stage. Further ECL-CMOS converters are known from the literature, for example from the publication IEEE ISSCC, 1986, pages 212-213, Static RAMs, THPM 16.6: "13ns/500 mw 64 kb ECL RAM" by Katsumi Ogiue et al, Hitachi Device Development Center, Tokyo, Japan. FIG. 3 of this publication discloses an ECL-CMOS converter that is composed of a symmetrical differential amplifier, of a level shifter and of a CMOS output stage. The ECL levels in this circuit fluctuate between -0.9 volts and -1.7 volts and are converted by the ECL-CMOS converter to a MOS level of 0.0 volts through -5.2 volts.
When a CMOS inverter stage is used in the output stage in the ECL-CMOS converter, the temperature and fluctuations in operating voltage have a very pronounced effect since the levels from the bipolar differential amplifier are referenced to the positive supply voltage, whereas the threshold of the CMOS amplifier always lies in the middle between the two supply voltages (approximately -2.5 volts).